Cypress Semiconductor PSoC® Microcontrollers
The PSoC® family of microcontrollers from Cypress are well-known for their flexible and configurable analog and digital blocks, providing great flexibility to embedded developers.
In conjunction with the iSYSTEM development environment, their PSoC® Creator remains the starting point for developers in order to configure these flexible modules. However, once complete, the power and insights that can be delivered by winIDEA and our BlueBox technology can be leveraged.
The dual-core PSoC® 6 family target IoT applications, handling activities requiring high-performance with the ARM® Cortex®-M4 core, leaving the Cortex®-M0+ core available for less demanding activities where power-consumption is the greater concern. On-chip peripherals, such as CapSense® and Bluetooth Low Energy (BLE) enable novel human-machine interfaces (HMI) with connectivity, whilst the in-built cryptography and secure memory regions make security possible, even whilst supporting multiple secure environments.
For driving segmented graphics displays, the PSoC® 5 is ideal, offering CapSense® and a variety of serial interfaces, including USB. Offered in chip-scale package (CSP), these devices are ideal for hand-held and wearable applications, making them suitable for fitness trackers and mobile devices. The Cortex®-M3 core has access to 24 channels of DMA, allowing efficient movement of data between peripherals and memory when required.
Featuring the Cortex®-M0 and M0+ cores, the PSoC® 4 family cover the cost-sensitive application space. Capacitive touch and BLE are offered in some sub-families, as are configurable analog blocks and programmable digital interfaces.
Both debug and program trace, where supported, are provided on these devices via ARM's CoreSight™ technology, utilizing the Serial Wire Debug (SWD) interface for pure debugging, Serial Wire Output (SWO) single-pin interface for basic trace output, and Embedded Trace Macrocell (ETM) 5-pin interface for advanced trace output.
An overview of the CoreSight™ features supported by this family are:
| CoreSight™ Feature | Description | PSoC 4 |
PSoC 4 |
PSoC 5 | PSoC 6 | iC5000 | iC5700 | |
| Cortex-M0 | Cortex-M0+ | Cortex-M3 | Cortex-M0+ | Cortex-M4 | ||||
| FPB (Flash Patch Breakpoint) | Implements hardware breakpoints | ✔ | ✔ | ✔ | ✔ | ✔ | ✔ | ✔ |
| DWT (Data Watchpoint and Trace) | Hardware comparators for program counter and data watchpoints |
✔ | ✔ | ✔ | ✔ | ✔ | ✔ | ✔ |
| ITM (Instrumentation Trace Macrocell) | Block supports printf style debugging, trace of RTOS events and output of diagnostic system information. |
✘ | ✘ | ✔ | ✘ | ✔ | ✔ | ✔ |
| ETM (Embedded Trace Macrocell) | 5-pin output for ITM or ETM trace messages | ✘ | ✘ | ✔ | ✘ | ✔ | ✔ | ✔ |
| MTB (Micro Trace Buffer) | Reserves SRAM to store trace information on-chip | ✘ | ✘ | ✘ | ✔ | ✘ | ✔ | ✔ |
| SWO (Serial Wire Output) | Single-pin output for ITM trace messages | ✘ | ✘ | ✔ | ✔ | ✔ | ✔ | ✔ |
| TPIU (Trace Port Interface Unit) | Bridge between on-chip trace data and either SWO or ETM interfaces. |
✘ | ✘ | ✔ | ✔ | ✔ | ✔ | ✔ |
| SWD (Serial Wire Debug) | Two-wire CoreSight™ interface used for debugging and debug configuration. |
✔ | ✔ | ✔ | ✔ | ✔ | ✔ | ✔ |
Via the Analyzer in winIDEA, embedded applications can be profiled for timing even when based upon a Real-Time Operating System (RTOS). And, if you are looking to improve code quality, the integrated testing tool testIDEA can also test your code and deliver code-coverage reports directly from code executed on the target microcontroller as well.
To get started, simply start your application in the "PSoC Creator" IDE, making use of the wealth of pre-existing peripheral drivers and software examples, then import the resulting project's ELF file into a winIDEA workspace. Getting started is made even easier with our Tutorial Getting started with winIDEA.