Trace Function

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Are there any issues that I have to be aware of while using the analyzer in the trace mode?
Can I do the following using the iC181? I have some ROM and RAM code, the ROM code is used at start-up and the RAM code contains information on device features. At power-up, the ROM code transfer to RAM code and in case of something goes wrong, it goes b
Can I set a qualifier on a variable write?
How does "Breakpoint by Trace Trigger" work?
I set a trigger on byte variable on address 0x5A12 but it doesn't work properly. Is there anything special to know? I use 186EC POD.
I use a HC12 POD and Power Trace. How is it possible to record with the analyzer the RTI instruction (Interrupt_function exit) and never have interrupt function entry when setting qualifier like below: Interrupt_function entry (0xF016) Interrupt_function
I use the analyzer in the trace mode. I use the 'Break on trigger' capability, but the CPU doesn't stop immediately after the trigger event. Why?
I use the HC12A4 POD and the analyzer in the trace mode. If I set trigger on a fetch/memory read cycle on the external data address, it doesn’t work.
I use the trace on my MC9S12DP256 Active POD. I'm trying to use 'watchdog timer' trace mode. I have two questions now. What is the minimum and maximum time that can be defined? What is the resolution of this timer?
I would like to set a trigger on a memory range, but it doesn't work. I entered the address from symbol table in the 'From' field (e.g. BUFRX_CH0). In the 'To' filed I entered the same symbol and I added 5 (e.g. BUFRX_CH0+5). This configuration doesn't w
I'm experiencing some problems using the Execution Coverage and a 186 POD. It does not appear to accurately reflect the actual execution. For instance, only one of two adjacent lines of code may be marked as executed, when logically both of them should b
If I use the 'Break on trigger' option, what's the delay between the trace trigger event and the moment when the application is actually stopped?
I’m experiencing some problems using the Z180 POD. In the attached WSB, the memory map for this project has RAM, starting at location 0x96000 physical, and 0x8000 logical. When trying to trace on the variable 'idle_timer, it doesn't seem to work. If the
I’m not able to trace the read from and/or the write to the internal CPU memory.
The trace trigger does not work if the variable being triggered on, is an integer that starts at an odd address boundary. For example, the customer has an integer at address 0x61A1. He sets the trace to trigger on address 0x61A1 when the data is 0x0008.
What are the Power Analyzer restrictions when emulating the expanded narrow mode?
Why profiler doesn’t work on the pipeline CPUs?


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