Cypress CYT2BL Emulation Adapter V1.6
Cypress CYT2BL Emulation Adapter is based on the 176-pin CYT2BL superset device and provides full trace capabilities for the
•64-pin
•80-pin
•100-pin
•144-pin
Traveo II CYT2BL Adaptation, where trace port is not available or lacks the full trace capability.
The Emulation Adapter might differ in some peripherals from the target device; therefore, the device datasheet should be checked. |
Cypress CYT2BL Emulation Adapter supports following debug and trace interfaces:
•JTAG or SWD debug interface
•MTB trace to trace Cortex-M0+ program execution; Trace data is stored in 4KB dedicated RAM memory and read out through JTAG or SWD;
•ETM/ITM trace to trace Cortex-M4 program execution; Trace data is connected to the external trace port (CPU port P18_4 – P18_7 or P22_0 – P22_3) which then connects to 20-pin 1.27mm CoreSight Debug Adapter
•ETB trace to trace Cortex-M4 program execution; Trace data is stored in 8KB dedicated RAM memory and read out through JTAG or SWD
•Serial wire viewer (SWV) and printf() style debugging through a Single Wire Output (SWO) “trace” pin on Cortex-M4
More information about our products via sales@tasking.com. |