Configuration
J1: Target reset configuration
Jumper J1 connects the Emulation Adapter reset line and the user target board reset line and is populated by default.
J2: TP20_2/TESTMODEn configuration
The TP20_2/TESTMODEn microcontroller pin is latched at power on reset release to enter test mode. Alternatively, it can operate as a general-purpose I/O.
The Solder jumper J2 connects the Emulation Adapter TP20_2/TESTMODEn signal with the microcontroller TP20_2 signal from the target. The microcontroller must not enter test mode during the Emulation Adapter operation. The J2 jumper is by default not connected preventing the microcontroller on the Emulation Adapter entering test mode at power-on reset if the target would be set up so. If the target uses this pin for I/O operation, solder the jumper J2 and double-check that the signal is properly conditioned at power-on reset.
Connector P1
It exposes DAP and AGBT interface.
Signal Direction |
Signal Description |
Signal |
Pin |
Pin |
Signal |
Signal Description |
Signal Direction |
|---|---|---|---|---|---|---|---|
I |
AGBT TX0_P |
TX0+ |
1 |
2 |
Vref |
Reference Voltage |
I |
I |
AGBT TX0_N |
TX0- |
3 |
4 |
DAP0 |
DAP clock |
O |
|
Ground |
GND |
5 |
6 |
DAP1 |
DAP Data pin |
I/O |
|
Not Connected |
NC |
7 |
8 |
NC |
Not Connected |
|
|
Not Connected |
NC |
9 |
10 |
DAP2 |
Optional 2nd Data pin |
I/O |
|
Ground |
GND |
11 |
12 |
nTRST/DAPEN |
JTAG/Output |
O |
|
Not Connected |
NC |
13 |
14 |
CLK+ |
AGBT Clock |
O |
|
Not Connected |
NC |
15 |
16 |
CLK- |
AGBT Clock |
O |
|
Ground |
GND |
17 |
18 |
TGO |
AGBT Trigger out |
I |
|
Not Connected |
NC |
19 |
20 |
AGBT ERR |
AGBT Error |
|
|
Not Connected |
NC |
21 |
22 |
RESET |
Reset |
I/O |
22-pin ERF8 AURIX pinout
Signal Direction is described from the BlueBox perspective.
Blue color marks the trace signals.
|
Be aware that debug and trace signals from the Emulation Adapter superset device are not connected to the target board. They are exposed only to the connectors on the Emulation adapter. |
