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winIDEA SDK
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Provides control functions for interacting with a specific core during a debug session.
This class allows users to perform various operations on individual cores, such as memory manipulation and core observation. It is typically used within the context of an active debug session and provides high-level access to core-specific functionality.
#include <CSessionCtrl.h>
Public Member Functions | |
| CCoreCtrl (SPConnectionMgr spConnectionMgr, const SHSC &rHSC) | |
| Constructs a CCoreCtrl instance for controlling a core in a debug session. | |
| void | memory_fill (uint8_t nMemoryArea, uint64_t nAddress, uint64_t nNumMAUs, const std::vector< uint8_t > &rvPattern) |
| Fills a specified memory area with a repeating pattern. | |
| std::vector< uint8_t > | memory_read (uint8_t nMemoryArea, uint64_t nAddress, uint64_t nNumMAUs, std::vector< uint8_t > *pvAccess=nullptr) |
| Reads data from a specified memory area. | |
| void | memory_write (uint8_t nMemoryArea, uint64_t nAddress, const std::vector< uint8_t > &rvData, std::vector< uint8_t > *pvAccess=nullptr) |
| Writes data to a specified memory area. | |
| void | observe (bool bObserve) |
| Enables or disables core observation within an active debug session. | |
| isys::CCoreCtrl::CCoreCtrl | ( | SPConnectionMgr | spConnectionMgr, |
| const SHSC & | rHSC ) |
Constructs a CCoreCtrl instance for controlling a core in a debug session.
Initializes core control by associating it with a connection manager and Struct Hardware(BlueBox)-SoC-Core index (SHSC). This object allows memory operations and core observation during debugging.
| spConnectionMgr | Shared pointer to the connection manager |
| rHSC | Reference to the SHSC |
| void isys::CCoreCtrl::memory_fill | ( | uint8_t | nMemoryArea, |
| uint64_t | nAddress, | ||
| uint64_t | nNumMAUs, | ||
| const std::vector< uint8_t > & | rvPattern ) |
Fills a specified memory area with a repeating pattern.
This method fills a memory region starting from the given address with a pattern of bytes. If the pattern is shorter than the specified number of memory access units (MAUs), it will be repeated to fill the entire region.
| nMemoryArea | Index of the memory area to use. |
| nAddress | Address at which to begin the memory fill operation. |
| nNumMAUs | Number of memory access units to fill. |
| rvPattern | The byte pattern to write into the memory. If shorter than nNumMAUs, it is repeated. |
| TException | if the operation fails. |
Python example: test_memory_fill.py
>>> conn_mgr = ic.ConnectionMgr()
>>> conn_mgr.connect()
>>> vect = ic.VectorBYTE([1, 2, 3, 4])
>>> sess_ctrl = ic.CSessionCtrl(conn_mgr)
>>> sess_ctrl.begin_reset()
>>> soc = sess_ctrl.get_SoC('')
>>> core_ctrl = soc.get_core(0)
>>> core_ctrl.memory_fill(0, 0x200000A0, 4, vect)
>>> vect = core_ctrl.memory_read(0, 0x200000A0, 4)
>>> [e for e in vect]
[1, 2, 3, 4]
| std::vector< uint8_t > isys::CCoreCtrl::memory_read | ( | uint8_t | nMemoryArea, |
| uint64_t | nAddress, | ||
| uint64_t | nNumMAUs, | ||
| std::vector< uint8_t > * | pvAccess = nullptr ) |
Reads data from a specified memory area.
Reads a sequence of bytes from the memory starting at the specified address. Optionally, access information can be returned for each accessed location.
| nMemoryArea | Index of the memory area to use. |
| nAddress | Address from which to begin reading data. |
| nNumMAUs | Number of memory access units to read. |
| pvAccess | (Optional) Pointer to a vector where access information for each accessed location is returned. |
| TException | if the operation fails. |
Python example: test_memory_read.py
>>> conn_mgr = ic.ConnectionMgr()
>>> conn_mgr.connect()
>>> vect = ic.VectorBYTE([1, 2, 3, 4])
>>> sess_ctrl = ic.CSessionCtrl(conn_mgr)
>>> sess_ctrl.begin_reset()
>>> soc = sess_ctrl.get_SoC('')
>>> core_ctrl = soc.get_core(0)
>>> core_ctrl.memory_fill(0, 0x200000A0, 4, vect)
>>> vect = core_ctrl.memory_read(0, 0x200000A0, 4)
>>> [e for e in vect]
[1, 2, 3, 4]
| void isys::CCoreCtrl::memory_write | ( | uint8_t | nMemoryArea, |
| uint64_t | nAddress, | ||
| const std::vector< uint8_t > & | rvData, | ||
| std::vector< uint8_t > * | pvAccess = nullptr ) |
Writes data to a specified memory area.
Writes a sequence of bytes into the memory starting at the given address. Optionally, access information can be provided for each accessed location.
| nMemoryArea | Index of the memory area to use. |
| nAddress | Address at which to begin writing data. |
| rvData | The data to write to the memory. |
| pvAccess | (Optional) Pointer to a vector where access information for each accessed location is returned. |
| TException | if the operation fails. |
Python example: test_memory_write.py
>>> conn_mgr = ic.ConnectionMgr()
>>> conn_mgr.connect()
>>> vect = ic.VectorBYTE([1, 2, 3, 4])
>>> sess_ctrl = ic.CSessionCtrl(conn_mgr)
>>> sess_ctrl.begin_reset()
>>> soc = sess_ctrl.get_SoC('')
>>> core_ctrl = soc.get_core(0)
>>> core_ctrl.memory_write(0, 0x200000A0, vect)
>>> vect = core_ctrl.memory_read(0, 0x200000A0, 4)
>>> [e for e in vect]
[1, 2, 3, 4]
| void isys::CCoreCtrl::observe | ( | bool | bObserve | ) |
Enables or disables core observation within an active debug session.
This operation is only valid while a session is active (e.g., after calling begin_reset()).
| bObserve | Set to true to enable core observation, or false to disable it. |
| TException | if the operation fails. |
Python example: test_observe.py
>>> conn_mgr = ic.ConnectionMgr()
>>> conn_mgr.connect()
>>> sess_ctrl = ic.CSessionCtrl(conn_mgr)
>>> sess_ctrl.begin_reset()
>>> soc = sess_ctrl.get_SoC('')
>>> core_ctrl = soc.get_core(0)
>>> core_ctrl.observe(True)