Arm Cortex-A MMU
In this topic:
Introduction
Core plugin shows memory-management unit (MMU) tables and their entries for the selected exception level (EL) or privilege level (PL) access.
The plugin can be loaded by selecting View | [<device>.COREn] Cortex-A | MMU.
Toolbar
Button |
Description |
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Extra commands |
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Automatically refresh all MMU views each time the CPU stops |
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Refresh all MMU views on command |
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Select the exception level you are interested in: •S3: secure EL3 (will read MMU table TTBR0_EL3) •NS2: non secure EL2 (will read MMU table TTBR0_EL2) •S1: secure EL1 (will read MMU tables TTBR0_EL1 and TTBR1_EL1) •NS1: non secure EL1 (will read MMU tables TTBR0_EL1, TTBR1_EL1 and VTBR0_EL2) •NS1 S1: non secure EL1 stage 1 (will read MMU tables TTBR0_EL1 and TTBR1_EL1) •NS1 S2: non secure EL1 stage 2 (will read MMU table VTBR0_EL2) |
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Go to winIDEA Help |
Memory Map window
Shows mapping from virtual or intermediate physical address to physical or intermediate physical address and common memory attributes for selected EL/PL(exception level, privilege level).
Toolbar
Button |
Description |
|---|---|
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Automatically refresh all MMU views each time the CPU stops |
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Refresh all MMU views on command |
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Go to winIDEA Help |
Translate Window
Translates entered VA to PA or PA to VA for selected EL/PL.
Example
On ARMv8 if EL “NS1” is selected, complete 2 stage translation will be made and PA will be returned. If “NS1 S1” is selected translation will be made from VA to IPA (only stage 1 will get translated).
