winIDEA Help

In this topic:

•Getting started

•Debug features

•Debug connectors

•Arm Cortex Architecture Overview

 

The information provided in this chapter is intended to be used together with the CPU reference manual provided by the silicon vendor. This chapter assumes knowledge of the CPU functionality and the terminology and concepts defined and explained in the CPU reference manual. Basic knowledge of winIDEA is also necessary. This chapter deals with specifics and advanced details and it is not meant as a basic or introductory text.

 

•CPU Options Configuration - Settings to prepare winIDEA for debug session.

•Debug - Access breakpoints, virtual memory access, breakpoints Wizard.

•Analyzer - Trace, Profiler and Coverage.

•Knowledge Base - Specific problems solved.

 

 

Getting started

Refer to Getting started Tutorials.

 

 

Debug features

 

 

Debug connectors

Not all debug protocol, trace protocol and debug connector combinations are possible. Debug Protocol is available unrelated to the used connector. Following table lists available trace protocols regarding to chosen Debug Protocol and Debug Adapter.

 

 

 

Arm Cortex Architecture Overview

Cortex-M CoreSight Debug and Trace Architecture

Arm CoreSight architecture allows debugging and tracing software that runs on a microcontroller or SoC. Trace data is typically captured off-chip but it can be also stored on-chip.

•OFF-CHIP - Trace data is first captured and then streamed via the BlueBox to the PC:

oParallel - Streams trace data via dedicated parallel trace pins

oSWO (Single Wire Output) - Streams trace data via single trace pin

 

•ON-CHIP - Trace data is recorded to the internal memory trace buffer and read through the debug interface. Buffer can be:

oETB - Embedded Trace Buffer

oMTB - Micro Trace Buffer

 

 

Cortex-M0+ Trace Architecture

Micro Trace Buffer (MTB) trace component is available on some Cortex-M0+ microcontrollers and provides a simple program trace capability. Trace data is saved to the trace buffer which is a dedicated area of the on-chip SRAM. The on-chip SRAM assigned to the MTB must not be used by the application while tracing. After trace data is saved, the BlueBox reads it out and reconstructs the program flow.

 

Limitations:

•Small buffer, typically between 2kB and 8kB

•No time information

•No data trace

 

 

Cortex-M3/4/7/33 Trace Architecture

Cortex-M3/4/7/33 based CPUs typically contain one or more trace components:

•ITM (Instrumentation Trace Macrocell) provides software instrumented trace (printf() style), timestamps for the ITM and the DWT trace messages and integrates the DWT trace messages into the trace stream.

•DWT (Data Watchpoint & Trace Unit) features interrupt trace, data trace, PC sampler and ETM trigger. The DWT output is fed into the ITM.

•ETM (Embedded Trace Macrocell) features program trace. ETM can act on events from the DWT. Trace capture methods supported on CortexM3/4/7/33 are:

•On-Chip: ETB

•Off-Chip: Parallel, SWO

 

 

Cortex-M Trace Components Overview

Cortex-M series of cores can feature different trace components. The table shows available trace components across different Cortex-M architectures.

 

 

 

More resources

•Arm Cortex - Microcontroller list, supported by winIDEA

•Documentation from Arm