This chapter explains Arm Cortex specific configuration for Trace, Profiler and Coverage analysis. For general analyzer information refer to general Analyzer chapter.

 

 

Trace

Tracing is possible in two ways:

•On-Chip Trace - Data is stored on dedicated internal buffers or in RAM (ETB, MTB, ETF…) and is downloaded from device through debug port (JTAG, SWD) or Debug Protocol.

•Trace port can be 1 to N width (Parallel, SWO). Tracing through trace ports is captured by debugger in real-time. winIDEA displays which trace method is supported on the device.

 

 

Operation mode

Before using trace for the first time please refer to the Analyzer chapter to learn more about trace technologies and possibilities. A selection between trace Analyzer Operation modes is done in the CPU Options dialog. Refer to Analyzer Configuration for more information.

 

 

Trace Capture method

Configuration of the Trace Capture method is described in the Setup chapter.

 

 

On-Chip Trace

Cortex-based CPUs can contain none, one or more on-chip trace sources which can all simultaneously be active and generate trace output. Cortex CPUs internally implement CoreSight component architecture provides a way to output multiple trace streams over a single trace port.

 

Cortex-based CPUs are populated with various combinations:

•Instrumentation Trace Macrocell (ITM) - Software instrumentation. Supported on Cortex-M. It provides “printf”-like trace ability using stimulus ports (memory mapped) to which target application can perform memory writes whose information is then output in a form of a trace packet in the ITM/DWT trace stream.

•Data Watchpoint and Trace (DWT) - Hardware event trace. Supported on Cortex-M. It provides a low bandwidth focused data trace using comparators to detect memory accesses and then generate trace packets with information about memory accesses.

•Embedded Trace Macrocell (ETM) - Instruction and/or data trace. Supported on Cortex-M, Cortex-A/R. Trace module comes in a couple of versions. Cortex-M ETM variants usually don’t feature data trace and own comparators. Cortex A/R ETM is usually fully featured.

•Micro Trace Buffer (MTB) - Program execution trace. Supported on Cortex-M0+.

•Program Trace Macrocell (PTM) - Instruction trace; mostly implemented on high performance Cortex-A devices.

•AHB Trace Macrocell (HTM) - Address and data trace of AHB bus. Supported on Cortex-M.

•System Trace Macrocell (STM)