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winIDEA Help

Version: 9.21.253

Use Cross Trigger Channels

Some MCUs feature cross trigger mechanism, which can be used either by the application (typically for diagnostic purposes) or the debug tool. winIDEA makes use of these channels to improve the debug and trace experience, but leaves an option to disable these features if your application needs these resources. Refer to the MCU's reference manual for more information on cross trigger mechanism. Open Hardware | CPU Options | SoC page.

 

CrossTriggering

 

 

0, 1 for synced Run/Stop

Multi-core systems are not synchronized by default. Channels 0 and 1 can be used to synchronize the run and stop actions of selected cores. These are used implicitly when the Debugging / Synchronize sellected cores option is enabled.

Note that the cores can only be configured once the debug logic becomes available. Some MCUs have debug logic available immediately after reset, but on some it becomes available only after the non-primary cores are released from reset. In these cases, the synchronization for each core separately is configured after it is stopped for the first time.

 

 

2, 3 for Trace Trigger and Flush

Trace Trigger

Cortex architecture does not feature a dedicated trace trigger signal, but it sends special trace packets instead. These need to be decoded, before winIDEA can react to the trigger, which would create a significant delay. Cross trigger channels can be used to trigger a special, easily detectable trace packet, which makes the trace trigger more prompt. Refer to Analyzer documentation for more information on trace triggers.

 

Trace Flush

If you are using a trace port and the CPU is stopped before the trace session is ended, some trace data remains in the trace component's FIFOs. Normally this data is flushed by winIDEA, but this method causes the remaining trace messages to arrive very late (with a noticeable time stamp delay), which poses a problem for timing measurements. A cross trigger channel can be used to automatically flush the trace component's FIFOs when the CPU stops.

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