Cypress Semiconductor Traveo Microcontrollers

The automotive industry demands functional safety and quality from its microcontrollers suppliers, making it sensible to utilize iSYSTEM's development environment with the family of Cypress Semiconductor's automotive MCUs.

The Traveo™ family targets motor control as used in hybrid and electric vehicles (HEV/EV), body electronics and instrument clusters. Featuring the ARM® Cortex®-R5 and R5F cores, these microcontrollers are available in both single and dual-core options. Innovative peripherals ensure that typically CPU-intensive tasks are taken on by dedicated hardware, with interfaces for motor sensor resolvers, a Secure Hardware Extension (SHE) for network security and a state-of-the-art 2D/3D graphics engine for head-up displays and instrument clusters.

The latest generation of automotive microcontrollers are in the Traveo™ II family, featuring a dual-core architecture. Featuring an ARM® Cortex®-M4 together with a Cortex®-M0+, the devices have up to 8MB of on-chip flash available designed to meet the stringent demands of automotive reliability requirements. In-vehicle networking is covered with CAN-FD, Ethernet and FlexRay, whilst an AUTOSAR 4.2 package eases development and integration efforts.

Both debug and trace support are provided on these devices via ARM's CoreSight™ technology, utilizing the Serial Wire Debug (SWD) interface for pure debugging, Serial Wire Output (SWO) single-pin interface for basic trace output, and Embedded Trace Macrocell (ETM) 5-pin interface for advanced trace output.

An overview of the CoreSight™ features supported by this family are:

CoreSight™ Feature Description Traveo™ Traveo™ II iC5000 iC5700
Cortex-M0+ Cortex-M4
FPB (Flash Patch Breakpoint) Implements hardware breakpoints
DWT (Data Watchpoint and Trace) Hardware comparators for program counter
and data watchpoints
ITM (Instrumentation Trace Macrocell) Block supports printf style debugging, trace of
RTOS events and output of diagnostic system
ETM (Embedded Trace Macrocell) 5-pin output for ITM or ETM trace messages
MTB (Micro Trace Buffer) Reserves SRAM to store trace information on-chip
SWO (Serial Wire Output) Single-pin output for ITM trace messages
TPIU (Trace Port Interface Unit) Bridge between on-chip trace data and either
SWO or ETM interfaces.
SWD (Serial Wire Debug) Two-wire CoreSight™ interface used for debugging
and debug configuration.

Via the Analyzer in winIDEA, embedded applications can be analysed for timing, even when based upon a Real-Time Operating System (RTOS). If you are looking to improve code quality, the integrated testing tool testIDEA can also test your code and deliver code-coverage report directly from execution on the target microcontroller as well.

Devices that do not feature a true hardware trace interface can use Emulation Adapter Cypress Traveo II featuring 176-pin CYT2B98CA superset device.

To get started, simply build your application using the software development environment provided with the Traveo™ family, making use of the wealth of pre-existing peripheral drivers and software stacks, then import the resulting project's ELF file into winIDEA workspace. Getting started is made even easier with our Tutorial Getting started with winIDEA.


Supported Mcus

S6J3 , S6J32xAxxC , S6J32xAxxD , S6J32xAxxE , S6J32xAxxF , S6J32xCxxC , S6J32xCxxD , S6J32xCxxE , S6J32xCxxF , S6J32xExxC , S6J32xExxD , S6J32xExxE , S6J32xExxF , S6J32xExxH , S6J331CJ , S6J331EJ , S6J331EK , S6J334DH , S6J334DJ , S6J334DK , S6J334EH , S6J334EJ , S6J334EK , S6J34x8 , S6J34x9 , S6J34xA , Traveo