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winIDEA Help

Version: 9.21.200

JTAG

This chapter explains JTAG clock and JTAG chain settings. Open Hardware / CPU Options / JTAG.

 

Warning_or

This page is hidden when Debug Protocol / Channel other than JTAG is selected in the SoC page.

 

OCDCortexCommon-CPUSetup-JTAG

 

Scan speed

Scan speed depends on the CPU clock and Target board PCB design.

 

info-icon

JTAG Scan speed 1000 kHz (default) should work in most cases. However, if the debug connection cannot be established with the Target  or the debug session behaves unreliably, try frequencies in the range from 1 to 5 MHz. A value in kHz can be manually typed in. If it still doesn’t work, go further below 1MHz until you find a working setting.

 

Number of idle TCKs

Define number of trailing TCK cycles after JTAG scan returns to Test-Logic-Idle JTAG state. Can be used to increase communication robustness at higher JTAG speeds.

 

Use Scan speed during Initialization

This option is useful on systems which start very slow. Slower scan speed can be used for first initialization sequence (see Initialization Sequence details), during which the CPU clock is raised (PLL engaged) and then higher scan speeds can be used for download and later while debugging.

 

Do not use TRST line - Enable this when assertion of JTAG TRST line is not desired. TAP will be reset only by clocking through Test-Logic-Reset JTAG state.

 

JTAG chain

Enable option This is the single device in the JTAG chain when only target CPU is connected to debug connector. Multiple TAPs inside target SoC are handled by winIDEA accordingly to CPU selection. Test Access Port (TAP) scan frequency is usually bound to target CPU system clock and it is couple of times slower.

 

When JTAG chain contains multiple TAPs the Instruction Register (IR) and (Data Register) DR prefixes and postfixes must be properly configured:

IR Prefix to the sum of IR lengths of all following* TAPs

IR Postfix to the sum of IR lengths of all preceding* TAPs

DR Prefix to the number of following* TAPs

DR Postfix to the number of preceding* TAPs

 

winIDEA can help detect the connected TAPs. Please refer to information about Hardware Tools JTAG chain dialog. There winIDEA reports detected IR offsets of detected TAPs which are same as IR Prefixes or offset from TDO of last* TAP.

* In a topology sense in direction from Test Data Input (TDI) to Test Data Output (TDO). Pre/post terminology was chosen based on when filling bits need be shifted into TDI.

 

 

Example of the JTAG chain

Note that the TDI from the JTAG Connector should be connected to the TDI of the first device in chain; and the TDO from the last device in chain should be connected to the TDO on the JTAG Connector.

 

OCDCortexCommon-JTAGchain

 

Target  

 

TAP

Target CPU TAP is

Setting          

TAP A

TAP B

TAP C

IR Prefix

5 + 3 = 8

3

0

IR Postfix

0

4

4 + 5 = 9

DR Prefix

2

1

0

DR Postfix

0

1

2

detection IR offset

5 + 3 = 8

3

0

 

 

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