TLB1
In this topic:
Introduction
The TLB1 plugin is a core plugin and shows the enhanced view of the Translation Lookaside Buffer (TLB1). The displayed columns correspond to the TLB entry bit definitions.
Select View | [SoC.COREn] PowerPC | TLB1 to load the plugin window. Information is displayed when a debug connection is established.
Toolbar
Button |
Description |
|---|---|
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Extra commands |
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Enable automatic update which is indicated by a [Rt] in the plugin title |
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Manual refresh |
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Shows descriptive values |
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Go to winIDEA Help |
Columns information
Column |
Description |
|---|---|
TS |
TS compared with process AS (address space) |
TID |
TID compared with process ID |
Virtual address |
Base Address seen by core |
Physical address |
Physical (bus) base address |
Size |
MMU page size |
VLE |
ISA used (VLE/PowerPC) |
Write-through |
Memory writes cannot be cached |
Cacheable |
Memory page can be cached |
Memory coherence |
Memory read/writes must be coherent with read/writes from other processors |
Guarded |
Loads/stores to memory region are performed without speculation |
Endianness |
Page access mode (big/little) |
Permissions |
Read, Write and Execute per execution mode (user, supervisor) |
G |
States, whether the accesses to this region are performed without speculation (i.e. they are known to be required) |
User bits |
Bits that can be used by SW |
Effective Page Number |
“virtual” page number |
Real Page Number |
“physical” page number |
Color information
Color |
Description |
|---|---|
Applicable to current process |
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Not applicable to current process |
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Clashes with another page |
