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winIDEA Help

Version: 9.21.150

Multi-core synchronization

This chapter describes how to synchronize core for AURIX devices. Multi-core synchronization can be achieved:

  • Automatically via Hardware / CPU Options / Debugging / Synchronize selected cores (stop/run) when possible or
  • Manually via SoC Debug Module.

 

For suspending peripheral devices refer to this chapter.

 

 

winIDEA Configuration

Multiple cores are hardware-wise not synchronized by default after reset. Synchronization can be optionally enabled by winIDEA. The option is ON by default.

 

number1

Open Hardware / CPU Options / Debugging.

 

number2

Make sure option Synchronize selected cores (stop/run) when possible is checked.

 

number3

For all cores you want to be a part of synchronization, check the Hardware / CPU Options / Cores / <Core> / Synchronize this core option.

 

 

Manual configuration

Synchronization can be achieved via a winIDEA configuration dialog of the on-chip OCDS module. For more information, refer to the OCDS chapter of the TriCore user manual. Open Hardware / SoC Debug Module.

 

TriCoreSoCdebugModule

Trigger Lines TL1-TL7

TriCore devices have internal 7 trigger lines to where Break, Suspend or Trigger Events from Cores, MCDS (trace) or Trigger Pins can be connected.

 

TL1 Suspend Targets

Simplified view of the Trigger line 1, which is used to suspend Targets.

 

CPUs

Each core has SUSIN, BRKIN, BRKOUT and HALT signals. For each core you can specify to which trigger line these signals are connected.

 

HSM / MCDS

Specify to which trigger line these signals are connected

 

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