NXP/ST Power Architecture
In this topic:
The information provided in this chapter is intended to be used together with the CPU reference manual provided by the silicon vendor. This chapter assumes knowledge of the CPU functionality and the terminology and concepts defined and explained in the CPU reference manual. Basic knowledge of winIDEA is also necessary. This chapter deals with specifics and advanced details and it is not meant as a basic or introductory text.
•Setup - General settings to prepare winIDEA for debug session
•Flash programming - Additional configuration settings for internal Flash programming.
•Analyzer - Trace, Aurora trace port, Trace templates, Profiler and Coverage.
•Knowledge Base - Specific problems solved.
Getting started
Refer to Getting started Tutorials.
Debug Features
•OnCe (JTAG) debug interface •Hardware execution breakpoints •Unlimited software breakpoints •Hardware data access breakpoints •FLASH programming •Multi-core support •Real-time memory access •SPT debugging (on devices where available) |
•Low power debug support •Hot Attach •MMU support •eTPU debugging •On-Chip Trace Buffer support (CPU dependent) •Parallel Nexus trace support (CPU dependent) •Aurora Nexus trace support (CPU dependent) |
Nexus trace
Nexus trace is explained separately for microcontrollers with Nexus Class 2+ and Nexus Class 3+ interface. Below table provides an overview of supported microcontrollers and trace related information.
