winIDEA HelpConfigure Architecture-specific settings
This tutorial explains how to configure minimum architecture specific settings required to connect BlueBox to the target microcontroller or SoC.
Your workspace should be configured and the correct SoC Device selected in Debug / Configure Session / SoCs.
Arm Cortex
Arm Cortex devices can feature multiple debug interfaces, SWD and JTAG being most common. The SWD debug interface is the preferred choice since it uses less physical pins and has higher data bandwidth.
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Open Hardware / CPU Options / SoC. |
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Select JTAG or SWD under the Debug Protocol. |
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Default SWD clock setting should work in most cases.
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(optional) Set JTAG Scan speed via Hardware / CPU Options / JTAG. |
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The page is visible only when the JTAG debug protocol is selected and confirmed. Default value 1000 kHz should work in most cases.
Infineon TriCore
TriCore devices can feature debug / trace interfaces:
•DAP (recommended) - Less physical pins and higher data bandwidth
oDAP Standard - One clock (DAP0) and one bidirectional data (DAP1) line
oDAP Wide (recommended) - One clock (DAP0) and two bidirectional data (DAP1 and DAP2) lines
•JTAG
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Open Hardware / CPU Options / SoC and select JTAG, DAP Standard, DAP Wide or DXCPL. |
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•JTAG - Additionally set JTAG Scan speed in Hardware / CPU Options / JTAG. The page is visible only when the JTAG debug protocol is selected and confirmed. Default value 1000 kHz should work in most cases.
•DAP Standard or DAP Wide - Default DAP Clock setting should work in most cases.
•DXCPL
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(optional) Set JTAG Scan speed via Hardware / CPU Options / JTAG. |
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(optional) Set a password. |
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Renesas RH850
RH850 devices feature one debug interface which is the LPD.
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(optional) Make sure LPD is set on the target device. |
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Use option Force FP5 Query before debug entry in Hardware / CPU Options / SoC Advanced to automatically set the device to LPD debug port.
Force FP5 Query before debug entry
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Set LPD clock in Hardware / CPU Options / SoC. |
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If the default LPD clock setting doesn’t work, it is recommended to lower the LPD clock below 4MHz. A value in kHz can be manually typed in.
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Enter matching security ID code. |
RH850 devices usually provide 128 or 256-bit Security ID code preventing an unauthorized access to the RH850 on-chip debugging resources through the debug interface.
A blank RH850 device out of the production comes with all bytes 0xFF in the Security ID code area.
NXP/ST Power Architecture
Power Architecture devices feature one debug interface which is the JTAG.
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Set JTAG Scan speed in Hardware / CPU Options / JTAG. |
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Default value 1000 kHz should work in most cases.
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(optional) Enter password via Hardware / CPU Options / SoC. |
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Some devices provide a 64-bit or a 256-bit password preventing an unauthorized access to the on-chip debugging resources through the debug interface.
Use password
More resources
•Architecture-specific notes in detail
Next steps
