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Version: 9.21.246

Configure Architecture-specific settings

In this topic:

Arm Cortex

Infineon TriCore

Renesas RH850

NXP/ST Power Architecture

 

 

Introduction

This tutorial explains how to configure minimum architecture specific settings required to connect BlueBox to the target microcontroller or SoC.

Your workspace should be configured and the correct SoC Device selected in Debug / Configure Session / SoCs.

 

 

Arm Cortex

Arm Cortex devices can feature multiple debug interfaces, SWD and JTAG being most common. The SWD debug interface is the preferred choice since it uses less physical pins and has higher data bandwidth.

 

number1

Open Hardware / CPU Options / SoC.

 

number2

Select JTAG or SWD under the Debug Protocol.

Default SWD clock setting should work in most cases.

 

arm-jtag-swd

 

number3

(optional) Set JTAG Scan speed via Hardware / CPU Options / JTAG.

The page is visible only when the JTAG debug protocol is selected and confirmed. Default value 1000 kHz should work in most cases.

 

arm-jtag-speed

 

 

Infineon TriCore

TriCore devices can feature debug / trace interfaces:

DAP (recommended) - Less physical pins and higher data bandwidth

oDAP Standard - One clock (DAP0) and one bidirectional data (DAP1) line

oDAP Wide (recommended) - One clock (DAP0) and two bidirectional data (DAP1 and DAP2) lines

JTAG

 

number1

Open Hardware / CPU Options / SoC and select JTAG, DAP Standard, DAP Wide or DXCPL.

JTAG - Additionally set JTAG Scan speed in Hardware / CPU Options / JTAG. The page is visible only when the JTAG debug protocol is selected and confirmed. Default value 1000 kHz should work in most cases.

DAP Standard or DAP Wide (recommended) - Default DAP Clock setting should work in most cases.

DXCPL

 

tricore-dap-jtag

 

number2

(optional) Set JTAG Scan speed via Hardware / CPU Options / JTAG.

 

tricore-jtag-speed

 

number3

(optional) Set a password.

 

 

Renesas RH850

RH850 devices feature one debug interface which is the LPD.

 

number1

(optional) Make sure LPD is set on the target device.

Use option Force FP5 Query before debug entry in Hardware / CPU Options / SoC Advanced to automatically set the device to LPD debug port.

 

number2

Set LPD clock in Hardware / CPU Options / SoC.

If the default LPD clock setting doesn’t work, it is recommended to lower the LPD clock below 4MHz. A value in kHz can be manually typed in.

 

number3

Enter matching security ID code.

RH850 devices usually provide 128 or 256-bit Security ID code preventing an unauthorized access to the RH850 on-chip debugging resources through the debug interface.

A blank RH850 device out of the production comes with all bytes 0xFF in the Security ID code area.

 

rh850-lpd

 

 

NXP/ST Power Architecture

Power Architecture devices feature one debug interface which is the JTAG.

 

number1

Set JTAG Scan speed in Hardware / CPU Options / JTAG.

Default value 1000 kHz should work in most cases.

 

number2

(optional) Enter password via Hardware / CPU Options / SoC.

Some devices provide a 64-bit or a 256-bit password preventing an unauthorized access to the on-chip debugging resources through the debug interface.

 

nxp-jtag-speed

 

 

More resources

Architecture-specific notes in detail

 

 

Next steps

Start a Debug Session

 

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