Red
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Colour
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Description
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Microcontroller Architecture
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Debug status
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winIDEA is connected to the BlueBox
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All
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ONLINE (READY TO ATTACH)
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Prepared to attach.
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NOT OBSERVED
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Core is not yet selected (automatically or by manual attach for (secondary cores) by the user) to be observed. Option in Hardware menu / Cores is unchecked.
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INACCESSIBLE
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Core debug info can not be determined.
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Renesas RH850
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Initial STOP
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Core is in Initial STOP state. Can be started via the BOOTCTRL register.
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Green
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Colour
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Description
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Microcontroller Architecture
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Debug status
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Core is in running state
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All
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RUN
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Core is running.
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Infineon TriCore
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RUN*
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Display of ''*'' after debug status is indication that MultiSoc Synchronization is active.
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Arm Cortex
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RUN [PC sampled address]
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Core is running and a program counter sampled address is optionally displayed.
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Renesas RH850
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RUN [Halt]
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Core is halted in low-power mode, the device cannot reliably return the reason.
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Dark green
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Colour
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Description
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Microcontroller Architecture
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Debug status
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Core in stopped, debug state
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All
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STOP
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Core is stopped.
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STOP*
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Display of ''*'' after debug status is indication that Multi Soc Synchronization is active.
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Arm Cortex
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STOP [CORE MODE] [STOP REASON]
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Stop status optionally if available displays a stop reason. Abbreviations are taken from ARM architecture reference manuals (e.g. STOP-VCATCH, STOP-BKPT).
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Infineon TriCore
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IDLE/PWRDOWN
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Core is in idle or power-down state.
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STOP [VMxSTOP REASON]
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The core is in the stop state and the currently active virtual machine number (x = 0–7) is reported with this status. The status also displays the stop reason if available. Abbreviations are taken from Infineon reference manuals (e.g. TRxEVT, SWEVT, etc.).
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Purple
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Colour
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Description
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Microcontroller Architecture
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Debug status
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Core is unreachable
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All
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RESET
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In reset mode either whole SoC or core internally.
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SoC RESET
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System reset is active. Debug session will tried to be started.
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ATTACHING
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Trying to reach either SoC level debug registers or core debug registers.
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SoC ATTACHING
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VREF is OK and system reset is released. Trying to reach the first SoC level debug registers to enable debug mode. Debug session will tried to be started.
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VREF
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No voltage from the target debug connector, which powers debug tool I/O buffers that physically drive the debug signals. Check Hardware | CPU Options | Hardware | Debug I/O levels.
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SoC NO POWER
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Vref checking is enabled and there is no Vref.
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NXP/ST Power Architecture
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HALTED
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Core is halted, reason is unknown.
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HALTED (CHKSTOP)
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Core is in Check Stop (Error) Mode.
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HALTED [halt reason
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Core is halted, reason is known (e.g. HALTED (HALT), HALTED (STOP), HALTED (WAIT) - Core is halted, because Halt/Stop/Wait instruction was executed).
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SOC RESET
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SoC was reset.
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Infineon TriCore
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SUSPENDED
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All activities stopped, core operation is suspended by other core.
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SUSPENDED*
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Display of ''*'' after debug status is indication that MultiSoc Synchronization is active.
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SUSPENDED [VMx]
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The core is in the suspended state and the currently active virtual machine number (x = 0–7) is reported with this status.
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TriCore TC3xx, TC4xx
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SUSPENDED (BHALT)
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Core operation is suspended by boot code (that is default state for secondary cores after reset).
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Renesas RH850
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HALTED
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Core is halted in low-power mode, Stop or Deep Stop. Some devices do not reliably return this status; winIDEA may show RUN even if the core has halted.
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HALTED [halt reason]
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Core is halted in low-power mode, reason is known, e.g. HALTED [Stop], HALTED [Deep Stop], etc.
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Renesas RH850
F1KM/KH
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PE1 DISABLED
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Special case after session Reset startup for the suspended cores PE1 and PE2 when ICUM is enabled and is tasked to release the PE1 and PE2.
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