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Navigation: Debug

Check Debug Status

Debug status display is located in the lower right corner of winIDEA and indicates whether the debug session is established and which is the current state of the core/SoC.

Table below explains possible states:

•Arm-specific

•TriCore-specific

•PowerPC (PPC)-specific

•RH850-specific

•ST-specific

•eTPU-specific

•SPT-specific

•Core modes

Some status strings include architecture-specific reasons. These reflect the target’s debug infrastructure, reflect vendor-specific descriptions. For more information, refer to the vendor documentation.

Generic (all architectures)

Status string	Description
NOT OBSERVED	Connection to the core(s) was not made
NOT OBSERVED Lockstep	Core is in a lockstep configuration with another core
NOT OBSERVED Error	Error occured when accessing the core
NOT ACCESSIBLE	Core is inaccessible
NOT ACCESSIBLE NoPower	Core has no (internal) supply
NOT ACCESSIBLE Condition	Condition for core access was evaluated to false
HALTED InReset	Core is in (internal) reset
RUN	Core is in running state
IDLE	Core is in idle state
SUSPENDED	Core is in suspended state
STOP	Core in debug-stop state

Arm-specific

Status string	Description
NOT ACCESSIBLE ARM_HDELow	Halting debug is not enabled.
NOT ACCESSIBLE ARM_SLKLocked	Software Lock is locked, unlocking did not succeed; Memory-mapped accesses to the external debug interface are not permitted.
NOT ACCESSIBLE ARM_OSLKLocked	OS Lock is locked; Another agent is using the debug infrastructure.
NOT ACCESSIBLE ARM_DLKLocked	OS Double Lock is locked; The core powerdown sequence is about to start.
NOT ACCESSIBLE ARM_Secure	External secure debug is disabled.
STOP HLT_RQ	Stopped due to HLT_RQ.
STOP VCT_CTCH	Stopped due to VCT_CTCH.
STOP SYNC_WP	Stopped due to SYNC_WP.
STOP RESTARTING	Core is restarting, exiting Debug state.
STOP BP	Stopped due to Breakpoint hit.
STOP EXT	Stopped due to an external debug request.
STOP STEP_NORM	Stopped due to halting step, normal.
STOP STEP_EXCL	Stopped due to the halting step, exclusive.
STOP OS_UNLCK	Stopped due to OS Unlock Catch.
STOP RST_CTCH	Stopped due to Reset Catch.
STOP WP	Stopped due to Watchpoint hit.
STOP HLT_INST	Stopped due to HLT instruction.
STOP SW_DBG_ACC	Stopped due to software access to the debug register.
STOP EXCP_CTCH	Stopped due to Exception Catch.
STOP STEP_NO_SYN	Stopped due to Halting step, no syndrome.
STOP DWTRAP	Stopped due to DWTRAP.

TriCore-specific

Status string	Description
STOP EXEVT	Stopped due to EXternal EVenT
STOP SWEVT	Stopped due to SoftWare EVenT (software breakpoint was hit)
STOP CREVT	Stopped due to Core Register access EVenT
STOP TRxEVT	Stopped due to TRigger x EVenT, where x=[0-7]

PowerPC (PPC)-specific

Status string	Description
HALTED PPC_HALT	Core is not clocked or is in low power state due to SoC low power mode (e.g. STANDBY0) or as a result of p_halt signal (e.g. initiated by SoC entering HALT0 low power mode).
HALTED PPC_STOP	Core is in Stopped low power state as a result of p_stop signal (e.g. initiated by SoC entering STOP0 low power mode).
HALTED PPC_CHKSTOP	Exception occurred, core triggering check stop state; core can be stopped for post-mortem analysis.
HALTED PPC_WAIT	Core executed wait instruction and entered Waiting low power state.

RH850-specific

Status string	Description
HALTED RH_HALT	On HALT instruction execution CPU enters HALT mode and halts instruction execution until reset, interrupt or exception.
HALTED RH_STOP	SoC in chip standby mode in which the clock supply to certain clocks can be stopped.
HALTED RH_DeepSTOP	SoC in chip standby mode to reduce power consumption further than STOP mode; In addition to the clock supply stop, the power supply to the Isolated area is switched off.
HALTED RH_CyclicRUN	Low-power operation mode in which limited modules can operate at low speed.
HALTED RH_CyclicSTOP	This is STOP chip standby mode in cyclic operation.

ST-specific

Status string	Description
HALTED STANDBY0	SoC in STANDBY0 mode
HALTED SmartPower	SoC in SmartPower mode
HALTED STOP	SoC in STOP mode

eTPU-specific

Status string	Description
NOT ACCESSIBLE ETPU_HALT	eTPU engine is in low power state.

SPT-specific

Status string	Description
IDLE SPT_RST	Command sequencer in RST state.
IDLE SPT_START	Command sequencer in START state
IDLE SPT_SETUP	Command sequencer in SETUP state
IDLE SPT_WAIT	Command sequencer in WAIT state
IDLE SPT_STOP	Command sequencer in STOP state
IDLE SPT_ASYNCSTOP	Command sequencer in ASYNCSTOP state

Core modes

Core mode may appear in the winIDEA Debug Status display and indicates the current execution context of the core The available modes depend on the target architecture and device configuration.

ARM – Cortex-M / Handler & Thread

Core mode	Execution context	Description
ARMvxM_Handler	Exception handler mode	Core is executing an exception handler.
ARMvxM_Thread	Thread mode	Core is executing normal application code.

ARM – AArch32

Core mode	Privilege	Security	Mode	Description
ARM_PL0S_usr	PL0	Secure	User	Unprivileged secure application code.
ARM_PL1S_fiq	PL1	Secure	FIQ	Secure fast interrupt handling.
ARM_PL1S_irq	PL1	Secure	IRQ	Secure interrupt handling.
ARM_PL1S_svc	PL1	Secure	Supervisor	Secure operating system code.
ARM_PL1S_abt	PL1	Secure	Abort	Secure abort exception handling.
ARM_PL1S_und	PL1	Secure	Undefined	Secure undefined instruction handling.
ARM_PL1S_sys	PL1	Secure	System	Secure privileged system execution.
ARM_PL0N_usr	PL0	Non-secure	User	Unprivileged non-secure application code.
ARM_PL1N_fiq	PL1	Non-secure	FIQ	Non-secure fast interrupt handling.
ARM_PL1N_irq	PL1	Non-secure	IRQ	Non-secure interrupt handling.
ARM_PL1N_svc	PL1	Non-secure	Supervisor	Non-secure operating system code.
ARM_PL1N_abt	PL1	Non-secure	Abort	Non-secure abort exception handling.
ARM_PL1N_und	PL1	Non-secure	Undefined	Non-secure undefined instruction handling.
ARM_PL1N_sys	PL1	Non-secure	System	Non-secure privileged system execution.
ARM_PL1S_mon	PL1	Secure	Monitor	Secure monitor mode (TrustZone control).
ARM_PL2N_hyp	PL2	Non-secure	Hypervisor	Hypervisor execution mode.

Arm – AArch64

Core mode	EL	Security	Description
AARCH64_EL0S	EL0	Secure	Secure user-level application execution.
AARCH64_EL0N	EL0	Non-secure	Non-secure user-level application execution.
AARCH64_EL1S	EL1	Secure	Secure operating system execution.
AARCH64_EL1N	EL1	Non-secure	Non-secure operating system execution.
AARCH64_EL2N	EL2	Non-secure	Hypervisor execution level.
AARCH64_EL3S	EL3	Secure	Secure monitor / firmware execution.

Arm – AArch32 (EL-based)

Core mode	EL	Security	Mode	Description
AARCH32_EL0N_usr	EL0	Non-secure	User	Non-secure user application code.
AARCH32_EL1N_sys	EL1	Non-secure	System	Non-secure privileged system execution.
AARCH32_EL1N_fiq	EL1	Non-secure	FIQ	Non-secure fast interrupt handling.
AARCH32_EL1N_irq	EL1	Non-secure	IRQ	Non-secure interrupt handling.
AARCH32_EL1N_svc	EL1	Non-secure	Supervisor	Non-secure OS execution.
AARCH32_EL1N_abt	EL1	Non-secure	Abort	Non-secure abort handling.
AARCH32_EL1N_und	EL1	Non-secure	Undefined	Non-secure undefined instruction handling.
AARCH32_EL1S_sys	EL1	Secure	System	Secure privileged system execution.
AARCH32_EL1S_fiq	EL1	Secure	FIQ	Secure fast interrupt handling.
AARCH32_EL1S_irq	EL1	Secure	IRQ	Secure interrupt handling.
AARCH32_EL1S_svc	EL1	Secure	Supervisor	Secure OS execution.
AARCH32_EL1S_abt	EL1	Secure	Abort	Secure abort handling.
AARCH32_EL1S_und	EL1	Secure	Undefined	Secure undefined instruction handling.
AARCH32_EL0S_usr	EL0	Secure	User	Secure user application code.
AARCH32_EL3S_sys	EL3	Secure	System	Secure firmware/system execution.
AARCH32_EL3S_fiq	EL3	Secure	FIQ	Secure firmware interrupt handling.
AARCH32_EL3S_irq	EL3	Secure	IRQ	Secure firmware interrupt handling.
AARCH32_EL3S_svc	EL3	Secure	Supervisor	Secure firmware supervisor execution.
AARCH32_EL3S_abt	EL3	Secure	Abort	Secure firmware abort handling.
AARCH32_EL3S_und	EL3	Secure	Undefined	Secure firmware undefined instruction handling.
AARCH32_EL3S_mon	EL3	Secure	Monitor	Secure monitor mode execution.
AARCH32_EL2N_hyp	EL2	Non-secure	Hypervisor	AArch32 hypervisor execution.

PowerPC (PPC)

Core mode	Privilege	Description
PPC_User	User	Core is executing user (problem-state) code.
PPC_Supervisor	Supervisor	Core is executing privileged system code.

RISC-V

Core mode	Privilege mode	Description
RV_M_mode	Machine	Core is executing machine-level firmware.
RV_S_mode	Supervisor	Core is executing operating system code.
RV_U_mode	User	Core is executing application code.

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