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winIDEA Help

Version: 9.21.246

Navigation: Debugging

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Debug Status

Debug status display is located in the lower right corner of winIDEA and indicates whether the debug session is established and which is the current state of the core/SoC.

 

Table below explains possible states:

Dark red

Red

Green

Dark green

Purple

 

 

Dark red

Colour

Description

Microcontroller Architecture

Debug status

 

winIDEA is not connected to the BlueBox

All

OFFLINE

 

 

Red

 

 


Colour

Description

Microcontroller Architecture

Debug status

 

winIDEA is connected to the BlueBox

All

ONLINE (READY TO ATTACH)

Prepared to attach.

NOT OBSERVED

Core is not yet selected (automatically or by manual attach for (secondary cores) by the user) to be observed. Option in Hardware menu / Cores is unchecked.

INACCESSIBLE

Core debug info can not be determined.

 

 

Green

 

 

 

 

Colour

Description

Microcontroller Architecture

Debug status

 

Core is in running state

All

RUN

Core is running.

Infineon TriCore

RUN*

Display of ''*'' after debug status is indication that MultiSoc Synchronization is active.

Arm Cortex

RUN [PC sampled address]

Core is running and a program counter sampled address is optionally displayed.

Renesas RH850

RUN [Halt]

Core is halted in low-power mode, the device cannot reliably return the reason.

 

 

Dark green

 

 

 

 

Colour

Description

Microcontroller Architecture

Debug status

 

Core in stopped, debug state

All

STOP

Core is stopped.

STOP*

Display of ''*'' after debug status is indication that Multi Soc Synchronization is active.

Arm Cortex

STOP [(CORE MODE)] [-STOP REASON]

Stop status optionally if available displays a stop reason. Abbreviations are taken from ARM architecture reference manuals (e.g. STOP-VCATCH, STOP-BKPT).

Infineon TriCore

IDLE/PWRDOWN

Core is in idle or power-down state.

STOP [VMx]

The core is in the stop state and the currently active virtual machine number (x = 0–7) is reported with this status.

 

 

Purple

 

 

 

 

Colour

Description

Microcontroller Architecture

Debug status

 

Core is unreachable

All

RESET

In reset mode either whole SoC or core internally.

SoC RESET

System reset is active. Debug session will tried to be started.

ATTACHING

Trying to reach either SoC level debug registers or core debug registers.

SoC ATTACHING

VREF is OK and system reset is released. Trying to reach the first SoC level debug registers to enable debug mode. Debug session will tried to be started.

VREF

No voltage from the target debug connector, which powers debug tool I/O buffers that physically drive the debug signals. Check Hardware menu /CPU Options / Hardware / Debug I/O levels.

SoC NO POWER

Vref checking is enabled and there is no Vref.

NXP/ST Power Architecture

HALTED

Core is halted, reason is unknown.

HALTED (CHKSTOP)

Core is in Check Stop (Error) Mode.

HALTED [halt reason

Core is halted, reason is known (e.g. HALTED (HALT), HALTED (STOP), HALTED (WAIT) -  Core is halted, because Halt/Stop/Wait instruction was executed).

SOC RESET

SoC was reset.

Infineon TriCore

SUSPENDED

All activities stopped, core operation is suspended by other core.

SUSPENDED*

Display of ''*'' after debug status is indication that MultiSoc Synchronization is active.

SUSPENDED [VMx]

The core is in the suspended state and the currently active virtual machine number (x = 0–7) is reported with this status.

TriCore TC3xx,  TC4xx

SUSPENDED (BHALT)

Core operation is suspended by boot code (that is default state for secondary cores after reset).

Renesas RH850

HALTED

Core is halted in low-power mode, Stop or Deep Stop. Some devices do not reliably return this status; winIDEA may show RUN even if the core has halted.

HALTED [halt reason]

Core is halted in low-power mode, reason is known, e.g. HALTED [Stop], HALTED [Deep Stop], etc.

Initial STOP

Core is in Initial STOP state. Can be started via the BOOTCTRL register.

Renesas RH850

F1KM/KH

PE1 DISABLED

Special case after session Reset startup for the suspended cores PE1 and PE2 when ICUM is enabled and is tasked to release the PE1 and PE2.

 

 

Troubleshooting

Refer to Knowledge Base.

 

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