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winIDEA Help

Version: 9.21.242

HSM Debugging

The HSM (Hardware Security Module) is an optional module available on selected Aurix devices.

 

Warning_orange

Read your Aurix device reference manual carefully. Use caution when debugging the HSM core as programming/erasing the HSM reserved FLASH sectors may result in locking the device. winIDEA offers few options which help you reducing the risk locking the device.

 

The HSM protection is configured in the User Configuration Block (UCB). Writing to UCB in winIDEA is disabled by default. UCBs serve as vital repositories of critical settings and configurations that drive the behavior and functionality of SoC features. They play a pivotal role in ensuring unmatched configurability.UCBs allow developers to define and configure crucial settings such as:

Reset vector

RAM initialization

Hardware Security Module (HSM) configuration

Logic Built-In Self-Test (LBIST)

FLASH protection

etc.

 

Warning_orange

Wrong UCB data can lock the device permanently. Use winIDEA Demo Mode prior flash programming to test whether all UCB sectors contain correct data.

Number of writes to UCB is limited. Refer to your TriCore device documentation for the exact number of writes. Uncheck <UCB_device> box once UCB is programmed.

 

Through winIDEA, you can program an HSM application and configure the UCB (User Configuration Block) which is required to enable the HSM on your Aurix device.

 

Warning_orange

It is recommended to use Image checker during UCB or HSM code programming.

HSM application programming and UCB configuration requires caution because a misconfiguration can potentially lock your chip.

 

number1

Enable UCB via Hardware / Options / Programming.

AURIX-UCBenable

 

number2

Make sure Automatically observe this core via Hardware / CPU Options / Cores HSM is checked.

 

number3

Open the secondary winIDEA instance via Debug / Core / HSM.

TriCore-HSM

 

Number4

Connect to the primary winIDEA instance via Debug / Connect.

When connected the Debug Status winIDEA is:

Primary:               [CPU0] STOP           

Secondary:               [HSM] STOP           

 

debug-connect

 

 

 

Next steps

Multi-core Debugging

Infineon TriCore AURIX TC3xx HSM - Debug & Timing Analysis - Webinar (Instrumenting HSM code and trace using MCDS data trace, Sampling-based Profiling)

 

 

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