winIDEA Help

In this topic:

•Enabling the SCR core via SoC DAP

•Debugging the SCR as a primary SoC

 

 

Introduction

A Standby Controller (SCR) is an 8-bit microcontroller based on 8051 architecture and can continue to run also during the standby mode. It's available on selected TC3xx devices. The SCR SoC is selectable for debugging in winIDEA as any other SoC.

 

Before you can start debugging the SCR core via SoC DAP or as the primary core via the Private DAP interface, the chip must be properly enabled and configured.

 

The SCR SoC can be debugged via:

•SoC DAP port (regular DAP debug port)

This port operates at up to 160 MHz frequency. When debugging the SCR SoC make sure you work at 10 MHz DAP clock or lower since this is the restriction of the SCR. Regular debugging of other AURIX cores through this port works up to 160 MHz DAP clock - if the embedded target is designed (PCB layout) properly.

 

Works with BlueBox debugger:

•iC5700 via Debug Adapter

•iC7max/iC5700 with an Infineon DAP/DAPE II Active Probe

•iC5000

 

•Private DAP port, called SCR DAP and has access to the SCR only. Other Aurix cores are not accessible through this port. Make sure you work at 10 MHz DAP clock or below.

 

Works with BlueBox debugger:

•iC5000 via Debug Adapter

•iC7max/iC5700

 

Before connecting the debugger, double check on the embedded target what DAP port is exposed on the physical debug connector.

 

SoC DAP port - Marked with yellow rectangle.

Private DAP port - Marked with green rectangle.

 

Enabling the SCR core via SoC DAP

Before you can start debugging the SCR core via the SoC DAP interface, the device must be properly configured.

 

 

The SCR core can be enabled via an initialization script, which is added to Hardware  / CPU Options / Reset / Initialization before Programming and configures two registers.

 

Script example:

 

Writing to the PMS_PMSWCR4 register via the initialization script enables the SCR and SoC DAP mode. Writing 0xFFFFFFFF to the PMS_PMSWSTATCLR register clears all status registers. All general purpose registers on the SCR core are memory mapped to first 255 bytes of the memory.

 

Standard SFR Symbols of the TC3xx

 

 

The SCR must start in one of the OCDS modes. Start-up is controlled by the SCRCFG bits in the Standby and Wake-up Control Register 4. When the SCR is started in OCDS SoC DAP mode, the SCR is considered as a secondary core in winIDEA and is debugged through the same (SoC) debug interface as all other TriCore/HSM cores.

 

 

 

Debugging the SCR as a primary SoC

When the SCR is started in OCDS SCR DAP mode, then the SCR debugging is possible via Private DAP interface. Target board must have a Private DAP debug connector where the debugger is connected to debug the SCR via Private DAP interface.

 

 

This will result in the SCR as the primary SoC.

 

To debug SCR core via private DAP, application running TriCore code must properly configure ports and PMS_PMSWCR4 register. The same can be also configured via INI file executed on the TriCore side.

 

Which debug pins are used is selectable in the PMS_PMSWCR4 register.

•If SCR debugging is done via SCR DAP0_0 and DAP1_0 pins, use the following INI file:

 

       Boot Modes

 

•If debugging via SCR_DAP0_1 pin and DAP1_1 pin is used, then use the following ini file: