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winIDEA Help

Version: 9.21.260

Debugging

Open Hardware | CPU Options | Debugging.

 

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This dialog allows SCR debugging via Private DAP.

 

Tricore-debugging

 

Synchronize selected cores (stop/run) when possible

Checked option configures available on-chip debug logic for cores to stop and run at the same time when debugging. If you want a specific core to be included in the synchronization, the Cores | <core> | Synchronize this core option must be checked as well.

 

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Note that all synchronization combinations might not be possible. The possibilities are determined by the target architecture, synchronization resources, SoC restrictions, etc.

Refer to the reference manuals and descriptions of used architecture and SoC for more information.

 

Set/clear SW BPs before Run

When the option is checked, then a software breakpoint is not set/cleared immediately, but is just remembered. Only when the CPU is set to running are the breakpoints committed. This way several breakpoints can be changed but only one re-FLASH operation takes place. This is especially noticeable in testIDEA operation with many stubs and also during a regular debugging session when several breakpoints are set/cleared within the same flash erase block.

 

Ignore Access errors

When checked, the debugger identifies memory access errors for individual memory location(s). When the option is unchecked, the debugger would declare access error for remaining memory locations once one access error is detected within a memory read block, which is used in the Disassembly window or memory window.

 

Cache downloaded code only (do not load to target)

When this option is checked, the download files will not propagate to the target using standard debug download but the Target download files will.

In cases, where the application is previously programmed in the target or it's programmed through the flash programming dialog, the user may uncheck Load code in the Properties dialog when specifying the debug download file(s). By doing so, the debugger loads only the necessary debug information for high level debugging while it doesn't load any code. However, debug functionalities like ETM and Nexus trace will not work then since an exact code image of the executed code is required as a prerequisite for the correct trace program flow reconstruction. This applies also for the call stack on some CPU platforms. In such applications, Load code option should remain checked and 'Cache downloaded code only - do not load to target (deprecated)' option checked instead. This will yield in debug information and code image loaded to the debugger but no memory writes will propagate to the target, which otherwise normally loads the code to the target.

 

Image checker (supported for TC2xx, TC3xx, TC4x)

Image checker analyzes the download file(s) at download in order to prevent misconfiguration of MCU, which could result in incorrect boot or bricked MCU due to disabled debug periphery. It distinguishes between

non-debuggable (secured) state - Destructive violations after which MCU would not be useful anymore due to disabled debug

non-destructive violations (e.g. bad Boot vector)

 

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HSM boot vector on TriCore is treated as a destructive violation.

Each class of violations has three options:

Allow programming -  executes download

Modify write data to keep device unsecured -  winIDEA tries to patch download data with correct values. If it is not possible, the operation is rejected

Reject programming  - prevents download.

 

winIDEA displays a warning in the Progress window about:

a warning if Patch is applied or

an error if programming is rejected

Session initialization will fail if programming is rejected

When Reject policy is selected, the warning becomes an error message and operation is aborted. Same happens when Modify is selected, but the configuration cannot be fixed automatically.

 

Optional Device Checks

Select optional image checks available before flash programming.

 

Checks Program entry is an option in the Edit options dialog, which checks if the program entry address is reachable. Entry point is considered as specified in the default download file, unless overridden in Hardware | CPU Options | Cores | Address (Preset PC after stopped in init).

 

 

Debug channel (cable connection)

Within this dialog (architecture depended) you can configure the settings for debugging the SCR SoC via Private DAP. Make sure you select a suitable DAP or SPD (Single Pin DAP) according to your application and target pin out. Note that SPD is not supported on the iC5000.

 

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In case you selected the DAP Debug channel you have to configure the Debug clock as well.

 

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