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Version: 9.21.239

Real-time Memory Access

In this topic:

Real-time access in the SFR Window

Real-time access to variables in cached areas


TriCore debug module supports real-time memory access. Watch Window’s Rt.Watch panes can be configured to inspect memory with minimum intrusion while the application is running. Optionally, Memory and Special Function Registers (SFR) Windows can be configured to use real-time access as well.



Real-time access in the SFR Window

In general it is not recommended to use real-time access for the SFR Window, because real-time access still means stealing some CPU cycles. As long as the number of real-time access requests stays low, this is negligible and doesn't affect the application. However, if you update all SFRs or Memory Window via real-time access, you may notice different application behavior due to stealing too many CPU cycles.



When a particular special function register needs to be updated in real-time:

1. Put it in the real-time Watch Window.

2. Enable real-time access in the SFRs Window.

3. Keep SFRs Window closed or open but with SFRs collapsed. This allows observing a special function register in real-time with minimum intrusion on the application.


Using “alternative” monitor access to update a memory location or a memory mapped special function register while the application is running works like this: the application is stopped, the memory is read and then the application is resumed. Hence the impact on real time execution is severe and use monitor access for 'update while running' only if you are aware of the consequences and can work with them.



Real-time access to variables in cached areas

If your variables are in the cached segment, you can’t use real-time access.



TriCore does not support real-time cache memory reads via Cerberus interface.


CPU is designed in the way that the debugger can read only the real memory, not what is inside the cache. To read the content of cache, CPU provides a dedicated instruction - CACHEA.W.

On some architectures (i.e. ARM Cortex, NXP/ST Power Architecture) it is possible to insert and execute an instruction. This is called instruction stuffing. However, theTriCore debug interface does not support instruction stuffing, therefore CACHEA.W instruction can be executed by CPU only.



1. Enable the Allow cache monitor execution option.

2. CPU should periodically execute CACHEA.W instruction for problematic variables. This forces the modified data in a cache line to be written back to main memory, which is why this can not be performed real-time.

3. Re-link the application so that non-cached RAM is used for this variable.

4. Disable caching.

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