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Version: 9.21.246

Overview

In this topic:

Emulation Memory

Debug Access Port (DAP/DAPE)

AURORA Gigabit (AGBT) Interface

Profiler

Coverage

 

 

Introduction

This topic explains TriCore specific configuration for Trace including Templates, Aurora Trace Port, Profiler and Coverage analysis. For general information refer to general Analyzer chapter.

 

Per default, TriCore target processors don’t provide trace functionality, which is often necessary during the development and test process. As an alternative, Infineon offers a dedicated pin compatible Emulation Device (ED), which features Nexus compliant on-chip trace (MCDS) in conjunction with the standard OCDS debug module, which is controlled by the external tool through the JTAG or DAP debug interface.

 

Emulation device can feature either:

Aurora trace port, where Nexus trace information is pushed immediately off-chip to the external debug tool

On-Chip Trace Buffer, where Nexus trace information is stored in a dedicated trace buffer until it’s full and then read through debug interface and uploaded to the PC for further analysis.

 

Devices may support one or both of these two trace technologies. Availability depends on the specific TriCore ED.

 

Figure below shows a simplified block diagram of a TC3xx emulation device, including MCDS on-chip trace infrastructure. The components within the grey box are only available on Emulation devices.

 

Click to enlarge

Simplified block diagram of a TC3xx emulation device

 

The main components of the MCDS trace infrastructure are:

Trace Multiplexer (MUX)

Processor Observation Block (POB)

Bus Observation Block (BOB)

Multi-Core Cross Connect (MCX)

Memory Controller (DMC)

Emulation Memory

Debug Access Port (DAP/DAPE)

AURORA Gigabit (AGBT) Interface

 

 

Emulation Memory

TC2xx/TC3xx

The structure of the Emulation Memory (EMEM) is shown above. The TCM tiles can be used for the following trace use cases:

 

Trace into EMEM until full, read-out via DAP or JTAG Interface - Described in Message Storage Control.

Trace Streaming via DAP Interface using EMEM Tiles for interim Buffering - Upload while Sampling - The available EMEM tiles are managed by the BlueBox tool in a way that allows a permanent streaming of trace data. This so-called Upload while Sampling (UWS) mode allows a virtually unlimited trace recording, assuming that the trace data generation rate (be the MCDS) is less or equal the data throughput via the DAP interface.

UWS is operational with a minimum of 2 EMEM tiles. However, it is recommended to allocate a minimum of 3 EMEM tiles to trace when using  UWS.

Trace Streaming via AGBT using a EMEM Tile as FIFO - The TCM tile is used as a FIFO within the AGBT trace data path. Only on a few AURIX derivatives TCM tiles are used as AGBT FIFO. Typically, the AGBT uses the two XTM files as FIFO.

 

TC4xx

The LMU storage RAM can be used for the following trace use cases.

 

Trace into EMEM until full, Read-out via DAP or JTAG Interface - This use case is described in Message Storage Control.

Trace Streaming via DAP Interface - Upload while Sampling - In this case, the SoC uses TBUF buffers that are a part of the MCDS as an interim buffer. The trace tool constantly reads out the trace data out of the buffers and uploads is to the host PC via USB or Ethernet communication.This mode allows for virtually unlimited trace recording, provided that the data is not generated faster than the tool is able to upload it.

Trace Streaming via SGBT - In this case the TBUF is used as a FIFO within the SGBT trace data path.

 

 

Debug Access Port (DAP/DAPE)

The DAP is an Infineon proprietary interface. It can be used as either:

2-pin (DAP0, DAP1) or

3-pin (DAP0, DAP1, DAP2) bi-directional

interface to communicate debug and trace information between the AURIX device and the tool.

 

The DAP pins are multiplexed with the standard JTAG pins and are available on every AURIX device (also Production Devices). Emulation devices of the TC3xx family also offer a second DAP interface, the so-called DAPE.

 

The DAP interface can operate at clock frequencies of up to 160MHz. The maximum applicable frequency depends on the hardware setup, i.e. target board layout (e.g. distance between device and DAP connected on the ECU). The BlueBox iC5700 allows access to either the DAP interface directly via:

DAP cable adapter

Active Probe

 

The operation mode and clock frequency can be configured in winIDEA via Hardware / CPU Options / SoC.

 

DAP interface is used for:

Debug control communication

Transport of trace data (Upload While Sampling)

 

 

AURORA Gigabit (AGBT) Interface

A high-speed Aurora (AGBT) interface from AMD is being used as a trace port on high-end (typically multi-core) microcontrollers, where previous trace port technology could no longer keep up with increased trace data bandwidth requirement. Note that a dedicated Aurora debug connector is provided on the target. Some emulation devices can broadcast on-chip trace information either to a dedicated on-chip trace buffer or to an external debug tool over the Aurora interface.

 

The AURORA Gigabit (AGBT) interface is a very-high bandwidth trace streaming interface. It uses differential signaling to achieve transfer bit rates of several Gbit/s (Gbps). On AURIX devices the AGBT bandwidth is:

up to 6.25 Gbps for TC4x

2.5 Gbps for TC2x and TC3xx.

 

This makes the AGBT interface suitable to perform unconditional program trace and OS trace on multiple CPUs simultaneously. However, as the interface runs at frequencies in the GHz range, high-frequency design rules need to be applied when using the AGBT interface on the target hardware.

 

The AURIX AGBT interface complies with the AURORA trace interface specification of the NEXUS 5001™ Forum Standard (http://nexus5001.org/)

 

The operation mode and clock frequency can be configured in winIDEA via the Hardware / CPU Options / Aurora.

 

Warning_orange

Some TriCore emulation devices (ED) provide Aurora trace port, which is supported by iC5700 with AGBT Active Probe.

 

Aurora Trace trigger

Aurora trace port features a USER_IO pin (pin 18 on the 22-pin AGBT connector), which is used by the debugger to receive the trigger signal. Trigger output signal (TRO) needs to be routed from the MCDS to this pin by means of configuring the MCU.

In order to route the trigger output to the aurora trace port, use an initialization script such as the one below, which routes trigger output signal through the MCU P32.6 pin. Note that the script must be adjusted if other MCU pin is physically connected to the USER_IO Aurora trace port pin.

 

// TRACE TRIGGER OUTPUT
A CBS_TOPR L 0x00040000 // TL4 connected to trigger out pin 4
                        // port P32.6
A CBS_TRMT L 0x00000004 // MCDS trigger out 0 connected to TL4
A CBS_TOPPS L 0x00000200 // trigger output pulse stretched
                        // to minimum 4PBs (max)
A P32_PDR0 L 0x30333333 // port P32.6 - pad driver characteristic
                        // set to speed grade 1 (max)
 
// DISABLE TRACE TIME WHEN CPU IS STOPPED
// Master CPU (CPU0) connects HALT output to TL2
// MCDS break_in connection
A CBS_TRMC L 0x00200000 //MCDS Break in is connected to TL2

 

 

Operation mode

Before using trace for the first time please refer to the Analyzer chapter to learn more about trace technologies and possibilities. A selection between trace Analyzer Operation modes is done in the CPU Options dialog. Refer to Analyzer Configuration for more information.

 

 

Trace Configuration

Configuration windows may differ slightly from the screen shots presented in the following chapters, as different TriCore devices provide different functionalities.

 

 

Profiler

Warning_orange

Profiler is available on TriCore Emulation Devices (ED) only.

 

Set Cycle duration in the Hardware / CPU Options / Analyzer dialog, before using the Profiler.

 

Profiler session time is limited by the physical size of the on-chip trace buffer. Per default profiler configures on-chip trace logic for recording the complete program flow. When a limited session time is an obstacle for the test process and not all application functions are required to be profiled, the on-chip trace can be configured to record only functions of interest. This generates less trace messages within the same time frame and the same physical on-chip trace buffer yields longer session time.

 

DAP and DAP2 debug interface features upload while sampling operation mode, which allows uploading the on-chip trace buffer while the application is still being recorded. When tracing events with low frequency, infinite profiler session is possible.

 

 

Coverage

Refer the Coverage Analysis chapter for Coverage theory, background and result interpretation. Refer to the Analyzer Configuration chapter for details on analyzer and coverage configuration.

 

Warning_orange

Coverage is available on TriCore Emulation Devices (ED) only.

 

 

Coverage Configuration

Coverage session time is limited by the physical size of the on-chip trace buffer. Per default coverage configures TriCore on-chip trace logic for recording the complete program flow. When a limited session time is an obstacle for the test process and not all application functions are required to be tested for coverage metrics, the on-chip trace can be configured to record only functions of interest. This generates less trace messages within the same time frame and the same physical on-chip trace buffer yields longer session time. Time information is irrelevant for the coverage and can be switched off. This will prolong the session time further more.

DAP and DAP2 debug interface features upload while sampling operation mode, which allows uploading the on-chip trace buffer while the application is still being recorded. When tracing events with low frequency, infinite coverage session is possible.

 

 

Simple use cases

TriCore on-chip trace logic is very complex to configure. winIDEA provides solutions that cover most use cases:

Built-in templates, which facilitate configuring on-chip trace logic for e.g. recording one function, 4 functions or a single data object.

Trace Wizard that covers settings for triggering on a simple event or triggering immediately

Automatic, which record everything

Program flow + Instrumentation

 

 

More resources

Trace Analyzer - Webinars

Synchronous Debug & Trace on two Infineon AURIX devices - Application Note

 

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