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winIDEA Help

Version: 9.21.307

How to Sync Debug

In this topic:

Requirements

Hardware Configuration

Master winIDEA Workspace Configuration

Slave winIDEA Workspace Configuration

Synchronized Debug Operation

 

 

Introduction

For synchronous debugging of two Infineon AURIX devices, two winIDEA Workspaces have to be created, a Master Workspace and a Slave Workspace. Add-on modules are optional and not an essential part of the sync setup. Both iC7max/iC5700 Hubs are connected via the FBridge cable which enables synchronous debug.

 

i-icon

The Sync Debug functionality is supported for Infineon TriCore architectures.

 

For a general overview, refer to Multi-SoC Synchronization.

 

Example setup with two iC7max BlueBox

Example setup with two iC7max BlueBox

 

 

Requirements

2x iC7max/iC5700 BlueBox Debuggers with Hub

Infineon DAP/DAPE II

Infineon AGBT Active Probes

2x Infineon AURIX targets

1x FBridge Cable

2x CAN/LIN Add-on modules (optional)

CAN Cable(s)

 

 

Hardware Configuration

number1

Setup and Configure Hardware for both BlueBox Debuggers.

 

number2

Connect BlueBox Debuggers via the FBridge synchronization port.

 

number3

Open the winIDEA Workspace intended to be the winIDEA Master Workspace.

 

 

Master winIDEA Workspace Configuration

You can freely choose which of the two AURIX devices will act as the Master and which as the Slave.

 

The DAP clock frequency should be set to a high clock rate for an optimized target status polling rate. A high target polling rate improves the sync debug latencies as well as the time synchronization between on-chip timestamp and the BlueBox timestamp. The maximum possible clock rate mainly depends on the DAP signal routing on the target board.

 

 

number3

Synchronize the Master in Hardware | Options | BlueBox Sync.

Select This winIDEA instance is synchronization master from the Synchronization drop-down menu.

Enable Synchronize time.

Define the path to the Slave workspace via Add.

 

HardwareOptionsBlueBoxSync

 

 

Number4

Perform Debug | Download or Debug | Load Symbols Only.

The Slave Workspace will open automatically.

After successful download and launch, the Debug Status is shown:

Master Workspace        STOP*          

Slave Workspace    ONLINE (ready to ATTACH)     

 

 

Number5

Configure the FNet Operation for the Active Probe in Hardware | FNet Operation | Active Probe.

Enable Recording is enabled from the start via the Qualifier button.

Check all the options to establish synchronization:

oStop on StopSync

oRun on RunSync

oUse fast status checking

oGenerate StopSync when stopped

 

FNetOperationsAPSettingsAGBT

 

 

Slave winIDEA Workspace Configuration

 

 

number3

Synchronize the Slave in Hardware | Options | BlueBox Sync.

Select Allow slave-sync operation in the drop-down menu.

Enable Synchronize time.

 

HardwareOptionsBlueBoxSyncAllowSlave

 

 

Number4

Perform Debug | Download or Debug | Load Symbols Only.

After successful download and launch, the Slave Workspace Debug Status shows be        STOP*         (same as Master Workspace).

 

Number5

Configure the FNet Operation for the Active Probe in Hardware | FNet Operation | Active Probe.

Enable Recording is enabled from the start via the Qualifier button.

Check all the options:

oStop on StopSync

oRun on RunSync

oUse fast status checking

oGenerate StopSync when stopped

 

FNetOperationsAPSettingsDAP

 

 

Synchronized Debug Operation

This section describes the basic synchronized debug operations and its Debug Statuses.  The * indicates that synchronized debug is currently active.

 

Action

Debug Status

Master

Slave

Download

   [CPU0] STOP*   

    STOP*   

Run Master

   [CPU0] RUN*  

    RUN*   

Run Slave

   [CPU0] RUN*  

    RUN*   

Breakpoint hit in Master

   [CPU0] STOP*   

   SUSPENDED*   

Breakpoint hit in Slave

   [CPU0] SUSPENDED*   

    STOP*   

 

 

Single-Step Operations

Single-Step operations on the Master do not have any effect on the Slave. The Slave remains in       SUSPENDED*      .  While in       SUSPENDED*     , single-step operations (source-level or assembly-level) are not possible. Single-Step is only possible when the SoC is in      STOP*      .

 

For more information about the statuses, refer to Debug Status.

 

 

More resources

FNet Communication Network

Sync Trace on two Infineon AURIX devices

 

 

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